? semiconductor components industries, llc, 2016 january, 2016 ? rev. 4 1 publication order number: CM2006/d CM2006 praetorian l-c lcd and camera emi filter array with esd protection product description the CM2006 connects between the vga or dvi?i port connector and the internal analog or digital flat panel controller logic. the CM2006 incorporates esd protection for all signals, level shifting for the ddc signals and buffering for the sync signals. esd protection for the video, ddc and sync lines is implemented with low?capacitance current steering diodes. all connector interface pins are designed to safely handle the high current spikes specified by iec?61000?4?2 level 4 ( 8 kv contact discharge). the esd protection for the ddc, sync and video signal pins is designed to prevent ?backdrive current? when the device is powered down while connected to a video source that is powered up. separate positive supply rails are provided for the video / sync signals and ddc signals to facilitate interfacing with low voltage video controller ics and microcontrollers to provide design flexibility in multi?supply?voltage environments. two schmitt?triggered non?inverting buf fers redrive and condition the hsync and vsync signals from the video connector (sync1, sync2). these buffers accept vesa vsis compliant ttl input signals and convert them to cmos output levels that swing between ground and v cc. two n?channel mosfets provide the level shifting function required when the ddc controller or edid eeprom is operated at a lower supply voltage than the monitor. the gate terminals for these mosfets (v cc_ddc ) should be connected to the supply rail (typically 3.3 v, 2.5 v, etc.) that supplies power to the transceivers of the ddc controller. features ? includes esd protection, level?shifting, buffering and sync impedance matching ? vesa vsis version 1 revision 2 compatible interface ? supports optional navi signalling requirements ? 7 channels of esd protection for all vga port connector pins. all pins meet iec?61000?4?2 level 4 esd requirements ( 8 kv contact discharge) ? very low loading capacitance from esd protection diodes on video lines (3 pf maximum) ? schmitt?t riggered input buffers for hsync and vsync lines ? bidirectional level shifting n?channel fets provided for ddc_clk & ddc_data channels ? backdrive protection on all lines ? compact 16?lead qsop package ? these devices are pb?free and are rohs compliant applications ? vga and dvi?i ports in: ? monitors ? tvs marking diagram device package shipping ? ordering information www. onsemi.com CM2006?02qr qsop?16 (pb?free) 2500/tape & ree l qsop16 qr suffix case 492 ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. CM2006?02qr = specific device code yy = year ww = work week cmdyyww CM2006 02qr
CM2006 www. onsemi.com 2 electrical schematic video_1 video_2 video_3 gnd sync_out2 gnd v cc_ddc v cc sync_out1 sync_in2 sync_in1 ddc_in2 ddc_in1 r t 3 4 5 6 9 12 13 15 1 8 14 16 ddc_out2 ddc_out1 11 10 byp r t 7 enable 2 package / pinout diagram top view 16 pin qsop v cc 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 enable video_1 video_2 video_3 gnd v cc_ddc byp sync_in2 sync_out1 sync_out2 sync_in1 ddc_in2 ddc_out2 ddc_out1 ddc_in1 table 1. pin descriptions lead(s) name description 1 v cc this is a supply input for the sync_1 and sync_2 level shifters, video protection and the ddc circuits. 2 enable active high enable. disables the sync buffer outputs when low. 3 video_1 video signal esd protection channel. this pin is typically tied one of the video lines between the control- ler device and the video connector. 4 video_2 video signal esd protection channel. this pin is typically tied one of the video lines between the control- ler device and the video connector. 5 video_3 video signal esd protection channel. this pin is typically tied one of the video lines between the control- ler device and the video connector. 6 gnd ground reference supply pin. 7 v cc_ddc this is an isolated supply input for the ddc_1 and ddc_2 level?shifting n?fet gates. 8 byp an external 0.22 f bypass capacitor is required on this pin. 9 ddc_in1 ddc signal input. connects to the video connector side of one of the ddc lines.signal output. 10 ddc_out1 ddc signal output. connects to the monitor ddc logic. 11 ddc_out ddc signal output. connects to the monitor ddc logic. 12 ddc_in2 ddc signal input. connects to the video connector side of one of the ddc lines 13 sync_in1 sync signal buffer input. connects to the video connector side of one of the sync lines. 14 sync_out1 sync signal buffer output. connects to the monitor sync logic. 15 sync_in2 sync signal buffer input. connects to the video connector side of one of the sync lines. 16 sync_out2 sync signal buffer output. connects to the monitor sync logic.
CM2006 www. onsemi.com 3 specifications table 2. absolute maximum ratings parameter rating units v cc_ddc and v cc supply voltage inputs [gnd ? 0.5] to +6.0 v dc voltage at inputs video_1, video_2, video_3 ddc_in1, ddc_in2 ddc_out1, ddc_out2 sync_in1, sync_in2, enable [gnd ? 0.5] to [v cc + 0.5] [gnd ? 0.5] to 6.0 [gnd ? 0.5] to 6.0 [gnd ? 0.5] to [v cc + 0.5] v operating temperature range ?40 to +85 c storage temperature range ?40 to +150 c package power rating (t a = 25 c) 500 mw stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. table 3. standard operating conditions parameter rating units operating temperature range ?40 to +85 c v cc 5 v functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability.
CM2006 www. onsemi.com 4 table 4. electrical operating characteristics (note 1) symbol parameter conditions min typ max units i cc_ddc v cc_ddc supply current v cc_ddc = 5.0 v 10 a i cc v cc supply current v cc = 5 v; sync inputs at gnd or v cc ; sync outputs unloaded 1 ma v cc = 5 v; sync inputs at 3.0 v; sync outputs unloaded 2.0 ma v f esd diode forward voltage i f = 10 ma 1.0 v v ih logic high input voltage v cc = 5.0 v; (note 2) 2.0 v v il logic low input voltage v cc = 5.0 v; (note 2) 0.5 v v hys hysteresis voltage v cc = 5.0 v; (note 2) 400 mv v oh logic high output voltage i oh = 0 ma, v cc = 5.0 v; (note 2) 4.0 v v ol logic low output voltage i ol = 0 ma, v cc = 5.0 v; (note 2) 0.15 v r out sync driver output resistance v cc = 5.0 v; sync inputs at gnd or 3.0 v 7 15 24 i in input current video inputs v cc = 5.0 v; v in = v cc or gnd 10 a sync_in1, sync_in2 inputs v cc = 5.0 v; v in = v cc or gnd 10 a i off level shifting n?mosfet ?off? state leakage current (v cc_ddc ? v ddc_in ) < 0.4 v; v ddc_out = v cc_ddc 10 a (v cc_ddc ? v ddc_out ) < 0.4 v; v ddc_in = v cc_ddc 10 a i backdrive current conducted from input pins when vcc is powered down. v cc < v input_pin ; (note 5) 10 a v on voltage drop across level?shifting n?mosfet when ?on? v cc_ddc = 2.5 v; v s = gnd; i ds = 3 ma 0.18 v c in_vid video input capacitance v cc = 5.0 v; v in = 2.5 v; f = 1 mhz 3 pf v cc = 2.5 v; v in = 1.25 v; f = 1 mhz 3.5 pf t plh sync driver l => h propagation delay c l = 50 pf; v cc = 5.0 v; input t r and t f < 5 ns 12 ns t phl sync driver h => l propagation delay c l = 50 pf; v cc = 5.0 v; input t r and t f < 5 ns 12 ns t r, t f sync driver output rise & fall times c l = 50 pf; v cc = 5.0 v; input t r and t f < 5 ns 3 ns v esd1 esd withstand voltage, sync_out pins only v cc = 5 v; (notes 3 and 4) 2 kv v esd esd withstand voltage v cc = 5 v; (notes 3 and 5) 8 kv product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 1. all parameters specified over standard operating conditions unless otherwise noted. 2. these parameters apply only to the sync drivers. note that r out = r t + r buffer . 3. per the iec?61000?4?2 international esd standard, level 4 contact discharge method. byp and v cc must be bypassed to gnd via a low impedance ground plane with a 0.22 f, low inductance, chip ceramic capacitor at each supply pin. esd pulse is applied between the applicable pins and gnd. esd pulses can be positive or negative with respect to gnd. applicable pins are: video_1, video_2, video_3, sync_in1, sync_in2, ddc_in1 and ddc_in2. all pins are esd protected to the industry standard 2 kv human body model (mil?std?883, method 3015). 4. this specification applies to the sync_out pins only. 5. applicable pins are: video_1, video_2, video_3, sync_in1, sync_in2, ddc_in1 and ddc_in2.
CM2006 www. onsemi.com 5 application information figure 1. typical application connection diagram notes: 1. the CM2006 should be placed as close to the vga or dvi?i connector as possible. 2. the esd protection channels video_1, video_2, video_3 may be used interchangeably between the r, g, b signals. 3. if differential video signal routing is used, the red, blue, and green signal lines should be terminated with external 37.5 resistors. 4. ?vf? are external video filters for the rgb signals. 5. supply bypass capacitors c1 and c2 must be placed immediately adjacent to the corresponding vcc pins. connections to the vcc pins and ground plane must be made with minimal length copper traces (preferably less than 5 mm) for best esd protection. 6. the bypass capacitor for the byp pin has been omitted in this diagram. this results in a reduction in the maximum esd withstand voltage at the ddc_out pins from 8 kv to 2 kv. if 8 kv esd protection is required, a 0.22 f ceramic bypass capacitor should be connected between byp and ground. 7. the sync buffers may be used interchangeably between hsync and vsync. 8. the emi filters at the sync_out and ddc_out pins (c5 to c12, and ferrite beads fb1 to fb4) are for reference only. the component values and filter configuration may be changed to suit the application. 9. the ddc level shifters ddc_in, ddc_out, may be used interchangeably between ddca_clk and ddca_data. 10. r1, r2 are optional. they may be used, if required, to pull the ddc_clk and ddc_data lines to vcc_5v when no vga card is connected to the vga monitor. if used, it should be noted that ?back current? may flow between the ddc pins and vcc_5v via these resistors when vcc_5v is powered down.
CM2006 www. onsemi.com 6 package dimensions qsop16 case 492?01 issue a e m 0.25 c a1 a2 c detail a detail a h x 45 dim max min inches a 0.053 0.069 b 0.008 0.012 l 0.016 0.050 e 0.025 bsc h 0.009 0.020 c 0.007 0.010 a1 0.004 0.010 m 0 8 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. 4. dimension d does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.005 per side. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.005 per side. d and e1 are determined at datum h. 5. datums a and b are determined at datum h. b l 6.40 16x 0.42 16x 1.12 0.635 dimensions: millimeters 16 pitch soldering footprint 9 18 d d 16x seating plane 0.10 c e1 a a-b d 0.20 c e 18 16 9 16x c m d 0.193 bsc e 0.237 bsc e1 0.154 bsc l2 0.010 bsc d 0.25 c d b 0.20 c d 2x 2x 2x 10 tips 0.10 c h gauge plane c a2 0.049 ---- 1.35 1.75 0.20 0.30 0.40 1.27 0.635 bsc 0.22 0.50 0.19 0.25 0.10 0.25 0 8 4.89 bsc 6.00 bsc 3.90 bsc 0.25 bsc 1.24 ---- max min millimeters l2 a seating plane on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 CM2006/d praetorian ? is a registered trademark of semiconductor components industries, llc. literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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